About Real Intent Breakthrough in logic verification. Funded by very experienced people from EDA |
Atrenta, Inc. The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs. |
CG-CoreEl Offers design services in the area of FPGA design, Embedded Design, PCB Design and ASIC design. |
ESNUG John Cooley's independent newsletter on Synthesis and related silicon design automation software. Originally the e-mail Synopsys Users Group (ESNUG). A compiled set of emails contributed by synthesis tool users and edited by John along with his columns a |
Forte Design Systems Develops software which aids your ASIC flow from design through verification. |
Icarus Verilog Interactive An Open Source interactive simulator frontend for Verilog and VHDL circuit simulation. |
Innoveda A merging of design software companies, which creates a complete PC based design environment. This includes everything from ASIC design to PCB design. |
NEF Design, Inc. Tools for FPGA design and testing, evaluation boards for FPGA prototyping, hardware and system design consulting. |
Tharas Systems, Inc. Tharas Systems, Inc. provides hardware accelerated RTL simulation for SoC, up to 1000x the performance of software based simulators. |
TransEDA Developers of innovative design verification and coverage software. |
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